Rev A and Rev B

	Rev A — perfboard	Rev B — PCB
Carrier	Stripboard ≈100 × 80 mm, 30 AWG wire	2-layer KiCad board, same outline
FPC sockets	Off-the-shelf ZIF breakouts soldered to the stripboard	Hirose FH12 directly on the board
Shift registers	DIP-16 in sockets	SSOP/TSSOP
Pull-ups	9-pin SIP networks	4 × 0603 arrays
Pico	Socketed on 2 × 20 female headers	Same — socketed, replaceable
Mounting	M2 holes drilled to match the sled	M2 holes on the same pattern, plus holes matching the X240 base-cover standoffs
Firmware	identical	identical
GPIO map	identical	identical

Rev B is a drop-in: same connector positions, same holes, same firmware. A Rev A build can be upgraded by swapping the board. That constraint is deliberate — it keeps one set of docs, one enclosure design and one firmware.

Rev B is jumpered, not hard-routed — and why

Which of the keyboard FPC’s 40 lines are drive, sense, VCC, GND, backlight and power button is unknown until probing (#28); the ClickPad’s pin count until #29. A board that hard-routes FPC pins to GPIO before that would be wrong on arrival. So Rev B gets the parts that are certain — the ZIF connectors, the 74HC165 chain with its pull-up arrays, the PS/2 pull-ups, the backlight MOSFET, decoupling, the Pico socket — and brings the unknowns to headers that sit side by side:

Header	Carries	Jumper to
`J_KB` 2 × 20	keyboard FPC lines 1–40, one per pin	`J_MAT`
`J_MAT` 2 × 17	DRV0–9 (GP0–GP9), SENSE0–19 (chain inputs), BL−, BL+, PWR_BTN, GND	`J_KB`
`J_TP` 1 × 12	ClickPad FPC lines 1–12	`J_PS2`
`J_PS2` 1 × 8	3V3, GND, PS2_DATA (GP21, pulled up), PS2_CLK (GP22), fallback DATA/CLK (GP19/20, DNP pull-ups), LED_A, GND	`J_TP`

After probing, ~30 short jumper wires (or a tiny “personality” board plugged across both headers) make the assignment. Sense lines 20–23 are pulled up but not headered in this revision: the documented ThinkPad matrices need ≤ 20 sense lines, and J_MAT is already 34 pins. A Rev C hard-routes the measured map and deletes the headers.

Rev B schematic blocks

Pico module — 2 × 20 header footprint, USB at the rear edge, RUN broken out to a tactile reset button, TP1/TP2/TP3 broken out to a 4-pin USB-C header.
Keyboard FPC — FH12-40S-0.5SH(55), bottom contact, on the edge facing the deck. All 40 lines go to J_KB; every pin is probeable there after assembly.
Sense chain — 3 × 74HC165, PL/CP bussed, Q7 → DS cascade, 100 nF each, three 4 × 10 kΩ arrays per chip (12 elements per chip; 8 used, spares tied off).
ClickPad FPC — FH12-12S-0.5SH(55) as the placeholder (a 12-pin socket accepts narrower cables if you align pin 1; confirm after #29). All lines go to J_TP.
PS/2 — 4.7 kΩ pull-ups on DATA (GP21) and CLK (GP22). Second pair on GP19/GP20 with unpopulated pull-ups, for the TrackPoint fallback.
Backlight — 2N7002, 10 kΩ gate, 100 kΩ pull-down, series resistor footprint, jumper selecting 3V3 or VBUS for the anode.
Power button / LED — GP27 with ESD-friendly 100 Ω series; GP28 → 100 Ω → LED header.
Decoupling and bulk — 10 µF near the Pico’s 3V3 pin, 100 nF per IC.

Rules and what the generated board is

2-layer, 100 × 80 mm. Netclass targets 0.20 mm track / 0.15 mm clearance, vias 0.6 / 0.3 mm; board minimums 0.127 mm (JLCPCB/PCBWay 2-layer capability). The router is given that room deliberately — at 0.25 / 0.18 it left FPC lines unrouted.
Freerouting routes all 202 connections (0 unrouted) in about three minutes at 100 passes. The back-side GND pour is added afterwards with island removal on, so it only adds copper; every connection is the router’s.
kicad-cli pcb drc on the routed board: no errors, no unconnected items. The only warnings are a few dangling vias — router GND vias whose pour-side copper was removed as an island; harmless, and a later revision can delete them.
Mounting: four M2 holes on the sled pattern (4 mm in from each corner) and three M2.5 holes for the X240 base-cover standoffs at placeholder positions (MEASURE — issue #44 fixes them).

Ordering

JLCPCB / PCBWay: 2-layer, 1.6 mm FR-4, HASL or ENIG (ENIG recommended for the 0.5 mm FPC pads), 5 boards ≈ $2 plus shipping. Allow 1–2 weeks.
Order the Hirose connectors and the SMD parts from DigiKey/Mouser or, cheaper, from LCSC in the same basket as a JLCPCB order.
out/pcb/bom.csv (from kicad-cli sch export bom, grouped by value and footprint) is the parts list to order from; add LCSC/DigiKey numbers in the basket. An interactive HTML BOM is not produced — InteractiveHtmlBom is not in the pinned KiCad image.

How the files are made

The board is generated, not drawn: hardware/pcb/netlist_model.py holds the parts, library names and nets; gen_schematic.py writes the .kicad_sch and gen_pcb.py the .kicad_pcb from it, so the two cannot disagree. Routing is done by freerouting from a Specctra DSN exported by KiCad’s Python API, then imported back; DRC, PDF, gerbers and drill files come from kicad-cli. All of that runs in the pinned kicad/kicad and freerouting images via ./dev build pcb. Edit the model, not the KiCad files.

Deliverables of milestone M7

hardware/pcb/x240_pico_rev_b.kicad_pro + schematic + PCB (generated, committed)
out/pcb/schematic.pdf, board.pdf, gerbers.zip + drill, position file, bom.csv
This page updated with the real ordering parameters and a bring-up log.

Assembly with a soldering iron is realistic: the hardest parts are the FH12 connectors (0.5 mm pitch — flux, drag-solder, magnification) and the SSOP shift registers. Everything else is 0603 or larger.